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2570js?avr?11/06 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 130 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non-volatile progra m and data memories ? in-system self-programmable flash, en durance: 10,000 write/erase cycles 32k bytes (atmega325/atmega3250) 64k bytes (atmega645/atmega6450) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? eeprom, endurance: 100 ,000 write/erase cycles 1k bytes (atmega325/atmega3250) 2k bytes (atmega645/atmega6450) ? internal sram 2k bytes (atmega325/atmega3250) 4k bytes (atmega645/atmega6450) ? programming lock for software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities a ccording to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, an d lock bits through the jtag interface ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? four pwm channels ? 8-channel, 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? universal serial interface wi th start condition detector ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? five sleep modes: idle, adc noise re duction, power-save, power-down, and standby ? i/o and packages ? 53/68 programmable i/o lines ? 64-lead tqfp, 64-pad qf n/mlf, and 100-lead tqfp ? speed grade: ? atmega325v/atmega3250v/atmega645v/atmega6450v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 8 mhz @ 2.7 - 5.5v ? atmega325/3250/645/6450: 0 - 8 mhz @ 2.7 - 5.5v, 0 - 16 mhz @ 4.5 - 5.5v ? temperature range: ? -40c to 85c industrial 8-bit microcontroller with in-system programmable flash atmega325/v atmega3250/v atmega645/v atmega6450/v preliminary summary
2 atmega325/3250/645/6450 2570js?avr?11/06 features (continued) ? ultra-low power consumption ? active mode: 1 mhz, 1.8v: 350 a 32 khz, 1.8v: 20 a (i ncluding oscillator) ? power-down mode: 100 na at 1.8v pin configurations figure 1. pinout atmega3250/6450 (oc2a/pcint15) pb7 dnc (t1) pg3 (t0) pg4 reset/pg5 vcc gnd xtal2 (tosc2) xtal1 (tosc1) dnc dnc (pcint26) pj2 (pcint27) pj3 (pcint28) pj4 (pcint29) pj5 (pcint30) pj6 dnc (icp1) pd0 (int0) pd1 pd2 pd3 pd4 pd5 pd6 pd7 avcc agnd aref pf0 (adc0) pf1(adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) dnc dnc ph7 (pcint23) ph6 (pcint22) ph5 (pcint21) ph4 (pcint20) dnc dnc gnd vcc dnc pa 0 pa 1 pa 2 dnc (rxd/pcint0) pe0 (txd/pcint1) pe1 (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 vcc gnd dnc (pcint24) pj0 (pcint25) pj1 dnc dnc dnc dnc (ss/pcint8) pb0 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc1a/pcint13) pb5 (oc1b/pcint14) pb6 pa 3 pa 4 pa 5 pa 6 pa 7 pg2 pc7 pc6 dnc ph3 (pcint19) ph2 (pcint18) ph1 (pcint17) ph0 (pcint16) dnc dnc dnc dnc pc5 pc4 pc3 pc2 pc1 pc0 pg1 pg0 index corner atmega3250/6450 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
3 atmega325/3250/645/6450 2570js?avr?11/06 figure 2. pinout atmega325/645 note: the large center pad underneath the qfn/mlf packages is made of metal and internally connected to gnd. it should be soldered or glued to the board to ensure good mechani- cal stability. if the center pad is left uncon nected, the package might loosen from the board. disclaimer typical values contained in this datasheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min and max values will be available afte r the device is characterized. pc0 vcc gnd pf0 (adc0) pf7 (adc7/tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) aref gnd avcc 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 49 32 31 30 (rxd/pcint0) pe0 (txd/pcint1) pe1 (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc2a/pcint15) pb7 (t1) pg3 (oc1b/pcint14) pb6 (t0) pg4 (oc1a/pcint13) pb5 pc1 pg0 pd7 pc2 pc3 pc4 pc5 pc6 pc7 pa7 pg2 pa6 pa5 pa4 pa3 pa0 pa1 pa2 pg1 pd6 pd5 pd4 pd3 pd2 pd1 (int0) (icp1) pd0 xtal1 (tosc1) xtal2 (tosc2) reset/pg5 gnd vcc index corner (ss/pcint8) pb0 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 atmega325/645 dnc
4 atmega325/3250/645/6450 2570js?avr?11/06 overview the atmega325/3250/645/6450 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architec- ture. by executing powerful instructions in a si ngle clock cycle, the atmega325/3250/645/6450 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. block diagram figure 3. block diagram program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd timing and control oscillator interrupt unit eeprom spi usart status register z y x alu portb drivers porte drivers porta drivers portf drivers portd drivers portc drivers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 vcc gnd xtal1 xtal2 control lines + - analog comp arator pc0 - pc7 8-bit data bus reset calib. osc data dir. reg. portc data register portc on-chip debug jtag tap programming logic boundary- scan data dir. reg. portf data register portf adc pd0 - pd7 data dir. reg. portg data reg. portg portg drivers pg0 - pg4 agnd aref avcc universal serial interface avr cpu porth drivers ph0 - ph7 data dir. reg. porth data register porth portj drivers pj0 - pj6 data dir. reg. portj data register portj
5 atmega325/3250/645/6450 2570js?avr?11/06 the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega325/3250/645/6450 provides the following features: 32/64k bytes of in- system programmable flash wit h read-while-write capab ilities, 1/2k bytes eeprom, 2/4k byte sram, 54/69 general purpose i/o lines, 32 general purpose working regis- ters, a jtag interface for boundary-scan, on-chip debugging support and programming, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, universal serial interface with start condi- tion detector, an 8-channel, 10-bit adc, a programmable watchdog timer with internal oscillator, an spi serial port, and five soft ware selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other ch ip functions until the ne xt interrupt or hard- ware reset. in power-save mode, the asynch ronous timer will continue to run, allowing the user to maintain a timer base while the re st of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc to minimize switching noise during adc conversions. in standby mode, the crys- tal/resonator oscillator is runni ng while the rest of the de vice is sleeping. this allows very fast start-up combined with low-power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip in-system re-programmable (isp) flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the applica- tion flash memory. software in the boot flash section will continue to run while the application flash section is updated, pr oviding true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega325/3250/645/6450 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega325/3250/645/6450 avr is supported with a full suite of program and sys- tem development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
6 atmega325/3250/645/6450 2570js?avr?11/06 comparison between atmega325, atmega3250, atmega645 and atmega6450 the atmega325, atmega3250, atmega645, and atmega6450 differs only in memory sizes, pin count and pinout. table 1 on page 6 summarizes the different configurations for the four devices. pin descriptions the following section describes the i/o-pin special functions. v cc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving ca pabilities than th e other ports. port b also serves the functions of various special features of the atmega325/3250/645/6450 as listed on page 66. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega325/3250/645/6450 as listed on page 69. port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source table 1. configuration summary device flash eeprom ram general purpose i/o pins atmega325 32k bytes 1k bytes 2k bytes 54 atmega3250 32k bytes 1k bytes 2k bytes 69 atmega645 64k bytes 2k bytes 4k bytes 54 atmega6450 64k bytes 2k bytes 4k bytes 69
7 atmega325/3250/645/6450 2570js?avr?11/06 current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega325/3250/645/6450 as listed on page 70. port f (pf7..pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if th e jtag interface is enabled, the pull-up resis- tors on pins pf7(tdi), pf 5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface. port g (pg5..pg0) port g is a 6-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are externally pulled low will source current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various special features of the atmega325/3250/645/6450 as listed on page 70. port h (ph7..ph0) port h is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port h output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port h pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port h pins are tri-stated when a reset condition becomes active, even if the clock is not running. port h also serves the functions of various special features of the atmega3250/6450 as listed on page 70. port j (pj6..pj0) port j is a 7-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port j output buffers have symmetric al drive characteristics with both high sink and source capability. as inpu ts, port j pins that are externally pulled low will source current if the pull-up resistors are activated. the port j pins are tri-stated when a reset condition becomes active, even if the clock is not running. port j also serves the functions of variou s special features of the atmega3250/6450 as listed on page 70. reset reset input. a low level on this pin for longer than the minimu m pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 16 on page 40. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier. avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter.
8 atmega325/3250/645/6450 2570js?avr?11/06 aref this is the analog reference pin for the a/d converter. resources a comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr.
9 atmega325/3250/645/6450 2570js?avr?11/06 register summary note: registers with bold type only available in atmega3250/6450. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved - - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved - - - - - - - - (0xfb) reserved - - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) reserved - - - - - - - - (0xf8) reserved - - - - - - - - (0xf7) reserved - - - - - - - - (0xf6) reserved - - - - - - - - (0xf5) reserved - - - - - - - - (0xf4) reserved - - - - - - - - (0xf3) reserved - - - - - - - - (0xf2) reserved - - - - - - - - (0xf1) reserved - - - - - - - - (0xf0) reserved - - - - - - - - (0xef) reserved - - - - - - - - (0xee) reserved - - - - - - - - (0xed) reserved - - - - - - - - (0xec) reserved - - - - - - - - (0xeb) reserved - - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved - - - - - - - - (0xe6) reserved - - - - - - - - (0xe5) reserved - - - - - - - - (0xe4) reserved - - - - - - - - (0xe3) reserved - - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - - (0xe0) reserved - - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) portj - portj6 portj5 portj4 portj3 portj2 portj1 portj0 82 (0xdc) ddrj - ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 82 (0xdb) pinj - pinj6 pinj5 pinj4 pinj3 pinj2 pinj1 pinj0 82 (0xda) porth porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 82 (0xd9) ddrh ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 82 (0xd8) pinh pinh7 pinh6 pinh5 pinh4 pinh3 pinh2 pinh1 pinh0 82 (0xd7) reserved - - - - - - - - (0xd6) reserved - - - - - - - - (0xd5) reserved - - - - - - - - (0xd4) reserved - - - - - - - - (0xd3) reserved - - - - - - - - (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) reserved - - - - - - - - (0xcd) reserved - - - - - - - - (0xcc) reserved - - - - - - - - (0xcb) reserved - - - - - - - - (0xca) reserved - - - - - - - - (0xc9) reserved - - - - - - - - (0xc8) reserved - - - - - - - - (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 data register 173 (0xc5) ubrr0h usart0 baud rate register high 176 (0xc4) ubrr0l usart0 baud rate register low 176 (0xc3) reserved - - - - - - - -
10 atmega325/3250/645/6450 2570js?avr?11/06 (0xc2) ucsr0c - umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 175 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 174 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 173 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) reserved - - - - - - - - (0xbc) reserved - - - - - - - - (0xbb) reserved - - - - - - - - (0xba) usidr usi data register 188 (0xb9) usisr usisif usioif usipf usidc us icnt3 usicnt2 usicnt1 usicnt0 189 (0xb8) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 190 (0xb7) reserved - - - - - - - - (0xb6) assr - - - exclk as2 tcn2ub ocr2ub tcr2ub 141 (0xb5) reserved - - - - - - - - (0xb4) reserved - - - - - - - - (0xb3) ocr2a timer/counter 2 output compare register a 140 (0xb2) tcnt2 timer/counter2 140 (0xb1) reserved - - - - - - - - (0xb0) tccr2a foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 138 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) reserved - - - - - - - - (0xac) reserved - - - - - - - - (0xab) reserved - - - - - - - - (0xaa) reserved - - - - - - - - (0xa9) reserved - - - - - - - - (0xa8) reserved - - - - - - - - (0xa7) reserved - - - - - - - - (0xa6) reserved - - - - - - - - (0xa5) reserved - - - - - - - - (0xa4) reserved - - - - - - - - (0xa3) reserved - - - - - - - - (0xa2) reserved - - - - - - - - (0xa1) reserved - - - - - - - - (0xa0) reserved - - - - - - - - (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) reserved - - - - - - - - (0x9c) reserved - - - - - - - - (0x9b) reserved - - - - - - - - (0x9a) reserved - - - - - - - - (0x99) reserved - - - - - - - - (0x98) reserved - - - - - - - - (0x97) reserved - - - - - - - - (0x96) reserved - - - - - - - - (0x95) reserved - - - - - - - - (0x94) reserved - - - - - - - - (0x93) reserved - - - - - - - - (0x92) reserved - - - - - - - - (0x91) reserved - - - - - - - - (0x90) reserved - - - - - - - - (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) reserved - - - - - - - - (0x8c) reserved - - - - - - - - (0x8b) ocr1bh timer/counter1 output compare register b high 124 (0x8a) ocr1bl timer/counter1 output compare register b low 124 (0x89) ocr1ah timer/counter1 output compare register a high 124 (0x88) ocr1al timer/counter1 output compare register a low 124 (0x87) icr1h timer/counter1 input capture register high 124 (0x86) icr1l timer/counter1 input capture register low 124 (0x85) tcnt1h timer/counter1 high 124 (0x84) tcnt1l timer/counter1 low 124 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 atmega325/3250/645/6450 2570js?avr?11/06 (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b - - - - - -123 (0x81) tccr1b icnc1 ices1 - wgm13wgm12cs12cs11cs10 122 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 - -wgm11wgm10120 (0x7f) didr1 - - - - - - ain1d ain0d 195 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 212 (0x7d) reserved - - - - - - - - (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 208 (0x7b) adcsrb -acme - - - adts2 adts1 adts0 193/211 (0x7a) adcsra aden adsc adate adi f adie adps2 adps1 adps0 210 (0x79) adch adc data register high 211 (0x78) adcl adc data register low 211 (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - (0x75) reserved - - - - - - - - (0x74) reserved - - - - - - - - (0x73) pcmsk3 - pcint30 pcint29 pcint28 pcint27 pcint26 pcint25 pcint24 56 (0x72) reserved - - - - - - - - (0x71) reserved - - - - - - - - (0x70) timsk2 - - - - - - ocie2a toie2 143 (0x6f) timsk1 - -icie1 - - ocie1b ocie1a toie1 125 (0x6e) timsk0 - - - - - - ocie0a toie0 96 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 57 (0x6c) pcmsk1 pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 57 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 57 (0x6a) reserved - - - - - - - - (0x69) eicra - - - - - -isc01isc0054 (0x68) reserved - - - - - - - - (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register [cal7..0] 29 (0x65) reserved - - - - - - - - (0x64) prr - - - - prtim1 prspi psusart0 pradc 37 (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 31 (0x60) wdtcr - - - wdce wde wdp2 wdp1 wdp0 45 0x3f (0x5f) sreg i t h s v n z c 11 0x3e (0x5e) sph stack pointer high 13 0x3d (0x5d) spl stack pointer low 13 0x3c (0x5c) reserved - - - - - - - - 0x3b (0x5b) reserved - - - - - - - - 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 0x37 (0x57) spmcsr spmie rwwsb - rwwsre blbset pgwrt pgers spmen 249 0x36 (0x56) reserved 0x35 (0x55) mcucr jtd - -pud - - ivsel ivce 51/66/222 0x34 (0x54) mcusr - - - jtrf wdrf borf extrf porf 43 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se 34 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr idrd/ocdr7 ocdr6 ocdr5 o cdr4 ocdr3 ocdr2 ocdr1 ocdr0 218 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 193 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi data register 153 0x2d (0x4d) spsr spif wcol - - - - - spi2x 153 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 151 0x2b (0x4b) gpior2 general purpose i/o register 24 0x2a (0x4a) gpior1 general purpose i/o register 24 0x29 (0x49) reserved - - - - - - - - 0x28 (0x48) reserved - - - - - - - - 0x27 (0x47) ocr0a timer/counter0 output compare a 96 0x26 (0x46) tcnt0 timer/counter0 95 0x25 (0x45) reserved - - - - - - - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 atmega325/3250/645/6450 2570js?avr?11/06 note: 1. for compatibility with future devices, reserved bits shoul d be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can ther efore be used on registers containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructio ns, 0x20 must be added to these addresses. the atmega325/3250/645/6450 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x24 (0x44) tccr0a foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 93 0x23 (0x43) gtccr tsm - - - - - psr2 psr10 98/145 0x22 (0x42) eearh - - - - - eeprom address register high 20 0x21 (0x41) eearl eeprom address register low 20 0x20 (0x40) eedr eeprom data register 20 0x1f (0x3f) eecr - - - - eerie eemwe eewe eere 20 0x1e (0x3e) gpior0 general purpose i/o register 24 0x1d (0x3d) eimsk pcie3 pcie2 pcie1 pcie0 - - -int055 0x1c (0x3c) eifr pcif3 pcif2 pcif1 pcif0 - - - intf0 56 0x1b (0x3b) reserved - - - - - - - - 0x1a (0x3a) reserved - - - - - - - - 0x19 (0x39) reserved - - - - - - - - 0x18 (0x38) reserved - - - - - - - - 0x17 (0x37) tifr2 - - - - - -ocf2atov2143 0x16 (0x36) tifr1 - -icf1 - -ocf1bocf1atov1125 0x15 (0x35) tifr0 - - - - - -ocf0atov096 0x14 (0x34) portg - - - portg4 portg3 portg2 portg1 portg0 82 0x13 (0x33) ddrg - - - ddg4 ddg3 ddg2 ddg1 ddg0 82 0x12 (0x32) ping - - ping5 ping4 ping3 ping2 ping1 ping0 82 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 81 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 81 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 81 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 81 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 81 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 81 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 81 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 81 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 81 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 80 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 80 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 80 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 80 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 80 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 80 0x02 (0x22) p o rta p o rta 7 p o rta 6 p o rta 5 p o rta 4 p o rta 3 p o rta 2 p o rta 1 p o rta 0 8 0 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 80 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 80 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 atmega325/3250/645/6450 2570js?avr?11/06 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2
14 atmega325/3250/645/6450 2570js?avr?11/06 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 mnemonics operands description operation flags #clocks
15 atmega325/3250/645/6450 2570js?avr?11/06 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
16 atmega325/3250/645/6450 2570js?avr?11/06 ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green. 3. for speed vs. v cc see figure 130 on page 292 and figure 131 on page 293. atmega325 speed (mhz) (3) power supply ordering code package type (1) operational range 8 1.8 - 5.5v atmega325v-8ai atmega325v-8au (2) atmega325v-8mi atmega325v-8mu (2) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) 16 2.7 - 5.5v atmega325-16ai atmega325-16au (2) atmega325-16mi atmega325-16mu (2) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, 14 x 14 x 1.0 mm, thin profile plastic quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm, quad flat no-lead/micro lead frame package (qfn/mlf) 100a 100-lead, 14 x 14 x 1.0 mm, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp)
17 atmega325/3250/645/6450 2570js?avr?11/06 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green. 3. for speed vs. v cc see figure 130 on page 292 and figure 131 on page 293. atmega3250 speed (mhz) (3) power supply ordering code package type (1) operational range 8 1.8 - 5.5v atmega3250v-8ai atmega3250v-8au (2) 100a 100a industrial (-4 0 c to 85 c) 16 2.7 - 5.5v atmega3250-16ai atmega3250-16au (2) 100a 100a industrial (-4 0 c to 85 c) package type 64a 64-lead, 14 x 14 x 1.0 mm, thin profile plastic quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm, quad flat no-lead/micro lead frame package (qfn/mlf) 100a 100-lead, 14 x 14 x 1.0 mm, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp)
18 atmega325/3250/645/6450 2570js?avr?11/06 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green. 3. for speed vs. v cc see figure 130 on page 292 and figure 131 on page 293. atmega645 speed (mhz) (3) power supply ordering code package type (1) operational range 8 1.8 - 5.5v atmega645v-8ai atmega645v-8au (2) atmega645v-8mi atmega645v-8mu (2) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) 16 2.7 - 5.5v atmega645-16ai atmega645-16au (2) atmega645-16mi atmega645-16mu (2) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, 14 x 14 x 1.0 mm, thin profile plastic quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm, quad flat no-lead/micro lead frame package (qfn/mlf) 100a 100-lead, 14 x 14 x 1.0 mm, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp)
19 atmega325/3250/645/6450 2570js?avr?11/06 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green. 3. for speed vs. v cc see figure 130 on page 292 and figure 131 on page 293. atmega6450 speed (mhz) (3) power supply ordering code package type (1) operational range 8 1.8 - 5.5v ATMEGA6450V-8AI atmega6450v-8au (2) 100a 100a industrial (-4 0 c to 85 c) 16 2.7 - 5.5v atmega6450-16ai atmega6450-16au (2) 100a 100a industrial (-4 0 c to 85 c) package type 64a 64-lead, 14 x 14 x 1.0 mm, thin profile plastic quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm, quad flat no-lead/micro lead frame package (qfn/mlf) 100a 100-lead, 14 x 14 x 1.0 mm, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp)
20 atmega325/3250/645/6450 2570js?avr?11/06 packaging information 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 64a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
21 atmega325/3250/645/6450 2570js?avr?11/06 64m1 2325 orchard parkway s an jose, ca 95131 title drawing no. r rev. 64m1 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, g 64m1 5/25/06 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 b 0.1 8 0.25 0.30 d d2 5.20 5.40 5.60 8 .90 9.00 9.10 8 .90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 b s c l 0.35 0.40 0.45 note: 1. jedec s tandard mo-220, ( s aw s ingulation) fig. 1, vmmd. 2. dimension and tolerance conform to a s mey14.5m-1994. top view s ide view bottom view d e marked pin# 1 id s eating plane a1 c a c 0.0 8 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm exposed pad, micro lead frame package (mlf)
22 atmega325/3250/645/6450 2570js?avr?11/06 100a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100a, 100-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp) c 100a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.17 ? 0.27 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.50 typ notes: 1. this package conforms to jedec reference ms-026, variation aed. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note
23 atmega325/3250/645/6450 2570js?avr?11/06 errata atmega325 rev. c ? interrupts may be lost when writing the timer registers in the asynchronous timer 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/ workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. atmega325 rev. b not sampled. atmega325 rev. a ? interrupts may be lost when writing the timer registers in the asynchronous timer 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/ workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. atmega3250 rev. c ? interrupts may be lost when writing the timer registers in the asynchronous timer 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/ workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. atmega3250 rev. b not sampled.
24 atmega325/3250/645/6450 2570js?avr?11/06 atmega3250 rev. a ? interrupts may be lost when writing the timer registers in the asynchronous timer 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/ workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. atmega645 rev. a ? interrupts may be lost when writing the timer registers in the asynchronous timer 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/ workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. atmega6450 rev. a ? interrupts may be lost when writing the timer registers in the asynchronous timer 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/ workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2.
25 atmega325/3250/645/6450 2570js?avr?11/06 datasheet revision history please note that the referring page numbers in this section are referring to this docu- ment. the referring revision in this section are referring to the document revision. rev. 2570j ? 11/06 rev. 2570i ? 07/06 rev. 2570h ? 06/06 rev. 2570g ? 04/06 rev. 2570f ? 03/06 rev. 2570e ? 03/06 1. updated table 125 on page 296. 2. updated note in table 125 on page 296. 1. updated table 33 on page 89. 2. updated table 47 on page 94, table 49 on page 94, table 54 on page 121, table 56 on page 122, table 59 on page 138 and table 61 on page 139. 3. updated ?fast pwm mode? on page 112. 4. updated features in ?usi ? universal serial interface? on page 181. 5. added ?clock speed considerations.? on page 188. 6. updated ?errata? on page 342. 1. updated ?calibrated internal rc oscillator? on page 28. 2. updated ?osccal ? oscillator ca libration register? on page 29. 3. added table 126 on page 296. 1. updated ?calibrated internal rc oscillator? on page 28. 1. updated ?errata? on page 340. 1. added addresses in register descriptions. 2. updated number of genearl purpose i/o pins. 3. correction of bitnames in ?r egister summary? on page 10. 4. added ?resources? on page 8. 5. updated ?power management and sleep modes? on page 33. 6. updated ?bit 0 ? ivce: interrupt vector change enable? on page 51. 7. updated introduction in ?i/o-ports? on page 58. 8. updated ?spi ? serial peripheral interface? on page 146. 9. updated ?bit 6 ? acbg: analog co mparator bandgap select? on page 194. 10 updated features in ?analog to digital converter? on page 196. 11. updated ?prescaling and conversion timing? on page 199. 12. updated ?atmega325/3250/645/6450 boot loader parameters? on page 257. 13. updated ?dc characteristics? on page 290.
26 atmega325/3250/645/6450 2570js?avr?11/06 rev. 2570d ? 05/05 rev. 2570c ? 11/04 rev. 2570b ? 09/04 rev. 2570a ? 09/04 1. mlf-package alternative changed to ?quad flat no-lead/micro lead frame package qfn/mlf?. 2. added ?pin change interrupt timing? on page 53. 3. updated ?signature bytes? on page 261. 4. updated table 121 on page 276. 5. added figure 123 on page 277. 6. updated figure 92 on page 204 and figure 116 on page 269. 7. updated algorithm ?enter programming mode? on page 264. 8. added ?supply current of i/o modules? on page 301. 9. updated ?ordering information? on page 17. 1. ?features (continued)? on page 2 updated. 2. table 10 on page 29 updated. 3. com01:0 renamed com0a1:0 in ?8-bit timer/counter0 with pwm? on page 83. 4. prr-bit descripton added to ?16-bit timer/counter1? on page 99, ?spi ? serial peripheral interface? on page 146, and ?usart0? on page 155. 5. ?part number? on page 220 updated. 6. ?typical characteristics ? preliminary data? on page 296 updated. 7. ?dc characteristics? on page 290 updated. 8. ?alternate functions of port g? on page 74 updated. 1. updated ?ordering information? on page 17. 1. initial revision.
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